Several electronic, opto-electronic and photonic devices can benefit, in terms of higher performance and added functionality, from precisely engineered doping and heterojunction profiles, at least for the most critical active layers. Such precisely engineered layers cannot be made with the junction-formation methods used by conventional CMOS technology.
Conventional CMOS processing, which has been extended to the sub-100 nm technology generations, essentially relies on ion-implantation and rapid thermal annealing to make increasingly shallower and higher doped junctions.
Low temperature epitaxial growth (selective or non-selective), which can be achieved through many techniques such as Molecular Beam Epitaxy (MBE) and Chemical Vapor Deposition (CVD), each with many sub-variants, is the only fabrication method capable of realizing the precise doping and heterojunction profiles needed by advanced devices.
SiGe (and SiGeC) BiCMOS has introduced the epitaxy of silicon-germanium (and silicon-germanium-carbon) films to the CMOS processing line. Even though SiGe BiCMOS is a monolithically integrated technology, the SiGe Heterojunction Bipolar Devices (HBTs) require many additional masks and processing steps, which simultaneously increase the complexity and cost. On the other hand, HBTs are made on their own active areas, and are not tightly integrated with the CMOS devices. This is a critical point to enable new devices with pattern density similar to that of pure CMOS technology.
Co-pending patent application Ser. No. 10/399,495 introduced a method of fabrication of photodiodes monolithically integrated with CMOS, which achieved the goal of a very tight integration of the devices comprising the epitaxial layer (part of the photo-diodes) with the CMOS devices. The method of fabrication disclosed in said co-pending application provides the guidelines for the insertion of epitaxial growth of device layers onto CMOS active areas, in a manner and at a point of the CMOS process flow, resulting in the following:                1. The insertion of the epitaxial growth step has minimal impact on the overall “Front End” and “Back End” standard process flow of CMOS devices, and on the operation of said CMOS devices.        2. The epitaxial layers suffer a minimal impact from the CMOS processing, because the epitaxial growth step is inserted after all high-temperature steps characteristic of CMOS “Front End” processing.        
Co-pending patent application Ser. No. 10/399,495 also mentions that the insertion point for the epitaxial growth process, being after all high temperature steps of the “Front End” processing of CMOS, is ideally suitable for the introduction of materials, other than SiGeC and related alloys, that have been demonstrated to be epitaxially compatible with silicon having the (100) or (111) crystallographic orientations. The list of materials includes (among many others) PbTe, ZnS, GaN, AlN, Al2O3, LaAlO3, Pr2O3, CeO2, CaF2, Sr2TiO4, etc.
Said co-pending patent application describes an exemplary implementation of the method of fabrication of devices on bulk silicon substrates. The present application provides more details about said method of fabrication and an explicit description of the implementation of said method of fabrication to thick-film silicon-on-insulator substrates.
The present application also discloses small variations and derivations of said method of fabrication to enable more types of devices comprising epitaxial layers, to be monolithically integrated with CMOS, for example, devices such as avalanche photo-diodes for light absorption, avalanche photo-diodes for light emission, vertically stacked multiple photo-diodes, Heterojunction Bipolar Devices and Photo-Heterojunction Bipolar Devices, Heterojunction Gunn Diodes, Heterojunction IMPATT Diodes, etc.
In the remainder of the present disclosure, “photo-diode” or “photo-diode layers” are used in a non-restrictive way, as to encompass avalanche photo-diodes that can absorb and/or emit light, and/or other optoelectronic/photonic epitaxial layers/devices that do not require avalanche processes for light absorption and emission. Similarly “pixel” and “pixel cells” should be construed to mean “cells” with one or more devices that can absorb and/or emit light. Such optoelectronic/photonic devices, made according to the method of fabrication of co-pending patent application Ser. No. 10/399,495, are described in Provisional Patent Application No. 60/591,658, filed on Jul. 28, 2004.